The present invention relates, in general, to logic gates, and more particularly, to differential emitter coupled logic (ECL) gates used in programmable time delay circuits.
Differential ECL gates are used in numerous applications where high speed logic is required. A differential ECL circuit comprises a differential receiver having one inverting and one non-inverting input, and a pair of outputs coupled to the differential receiver. A typical differential receiver comprises a pair of differentially coupled transistors having emitters which are tied together. A base of one transistor is coupled to the non-inverting input of the differential circuit, while the base of the other transistor is coupled to the inverting input. Collectors of the differentially coupled transistors are coupled through resistors to a power supply voltage V.sub.cc. Emitters of the differential receiver transistors are coupled through a current source to a second power supply V.sub.EE which is at a lower potential than V.sub.CC. The differential outputs are coupled to the collectors of the differentially coupled transistors so that an input received at the base of one of the differentially coupled transistors results in an inverted output on one of the differential outputs.
Each leg of the differential receiver comprises one of the differentially coupled transistors together with its collector resistor. Current flow through each leg is a function of a voltage difference between the two differential inputs. One feature of the differential receiver is that current flow is rapidly switched from one leg to the other when voltage on the differential inputs is reversed. Usually this current switching occurs almost entirely within a few tens of millivolts in differential voltage.
A result of this switching characteristic is that when a logic state change occurs at the differential inputs, the differential outputs will remain steady until the differential input voltage passes through a zero point. This point is also referred to as a switching point of the circuit. As the differential input voltage approaches zero, the differential output voltage begins to change. A time lag results between the instant the outputs begin to change in response to a change in inputs, and a time when the input transistors of a sequentially coupled ECL circuit begin to respond. This time lag is called a propagation delay time (t.sub.pd) for the circuit.
Although ECL logic gates with differential inputs have a very low propagation delay in the range of a few hundred picoseconds, until now this propagation delay has been fixed and not controllable by the user of the logic circuit. Oftentimes it is desirable that the propagation delay be programmable via an external signal to the logic circuit. Until now this need could only be met by coupling two or more logic circuits in series to provide multiple gate delays. This solution increases size, and therefore cost of the logic circuit.
Accordingly, it is an object of the present invention to provide an ECL logic circuit having a variable propagation delay.
It is another object of the present invention to provide an ECL logic circuit having differential inputs and differential outputs wherein the response of each of the differential outputs can be controllably delayed.
A further object of the present invention is to provide a differential input ECL logic circuit having a feedback differential receiver which can controllably change an output voltage swing of the circuit to increase propagation delay.